In modern high density memories, such as random access memories having one Megabit or more, the time and equipment required to test functionality and timing of all bits in the memory constitute a significant portion of the RAM die fabrication cost: Accordingly, as the time required for such testing increases, the manufacturing costs also increase. Similarly, if the time required for the testing of memory can be reduced, then the manufacturing cost of the memory is reduced. Since the manufacturing of memory devices is generally done in high volume, the savings of even a few seconds per device can result in significant costs reduction.
Random access memories (RAMs) are especially subject to having significant test costs, not only because of the necessity of both writing data to and reading data from each bit in memory, but also because RAMs are often subject to pattern sensitivity failures. Pattern sensitivity failures arise because the ability of a bit to retain a stored data state may depend upon the data states stored in, and the operations upon, bits which are physically adjacent to that bit being tested. This causes the test time for RAMs to be not only linearly dependent upon die density (i.e., the number of bits available for storage) but, for some pattern sensitivity tests, also dependent upon the square (or 3/2 power) of the number of bits in the memory. Obviously, therefore, as the density of RAM devices increases (generally by a factor of four, from generation to generation), the time required to test each device in production rapidly increases.
It should be noted that many other integrated circuit devices, besides memory chips, themselves utilize memories on-chip. Examples of such integrated circuits include many modem microprocessors and microcomputers, as well as custom devices such as gate arrays which have memory embedded therein. Similar cost pressures are faced in the production of these products as well, including the time and equipment required for testing of the memory portions.
One solution which has been used to reduce the time and equipment required for the testing of semiconductor memories such as RAMs is to employ special "test" modes, where the memory enters a special operational state different from its normal operational mode. In such test modes, the operation of the memory can be quite different from that of normal operation, since the operation of internal testing can be done without being subject to the constraints of normal operation.
An example of a special test mode is an internal "parallel," or multibit, test mode. Conventional parallel test modes allow access to more than one memory location in a single cycle, with common data written to and read from the multiple locations simultaneously. For memories which have multiple input/output terminals, multiple bits would be accessed in such a mode for each of the input/output terminals in order to achieve the parallel test operation. This parallel test mode of course is not available in normal operation, since the user must be able to independently access each bit in order to utilize the full capacity of the memory. Such parallel testing is preferably done in such a way so that the multiple bits accessed in each cycle are physically separated from one another to ensure that there is little likelihood of pattern sensitivity interaction among the simultaneously accessed bits. A description of such parallel testing may be found in McAdams et at., "A 1-Mbit CMOS Dynamic RAM With Design-For-Test Functions," IEEE Journal of Solid-State Circuits, Vol SC-21, No. 5, pp. 635-642 (October 1986).
Other special test modes may be available for particular memories. Examples of tests which may be performed in such modes include the testing of memory cell data retention times, tests of particular circuits within the memory such as decoders or sense amplifiers, and the interrogation of certain portions of the circuit to determine attributes of the device such as whether or not the memory has had redundant rows or columns enabled. The above-referenced article by McAdams et al. describes these and other examples of special test functions.
Of course, when the memory device is in such a special test mode, it is not operating as a fully randomly accessible memory. As such, if the memory is in a test mode by mistake, for example when installed in a system, data cannot be stored and retrieved as would be expected. By way of example, when in parallel test mode, the memory should write the same data state to a plurality of memory locations. Accordingly, when presented with an address in parallel test mode, the memory will output a data state which does not depend solely on the stored data state, but may also depend upon the results of the parallel comparison. Furthermore, the parallel test mode necessarily reduces the number of independent memory locations to which data can be written and retrieved, since four, or more, memory locations are simultaneously accessed. It is therefore important that the enabling of the special test modes be accomplished in such a manner that the chance is low that a special test mode will be inadvertently entered.
Prior techniques for entry into special test modes include the use of a special terminal for indicating the desired operation. More particularly, a simple prior technique for the entry into test mode is the presentation of a logic level, high or low, at a dedicated terminal to either select the normal operation mode or a special operation mode such as parallel test, as described in U.S. Pat. No. 4,654,849. Another approach for the entry into test mode using such a dedicated terminal is disclosed in Shimada et al., "A 46-ns 1-Mbit CMOS SRAM," IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, pp. 53-58 (February 1988), where a test mode is enabled by the application of a high voltage to a dedicated control pad while performing a write operation. These techniques are relatively simple but they of course require an additional terminal besides those necessary for normal memory operation.
While such an additional terminal may be available when the memory is tested in wafer form, significant test time also occurs after packaging, during which special embedded test modes are useful. In order to use this technique of a dedicated test enable terminal for package test, it is therefore necessary that the package have a pin or other external terminal for the function. However, due to the desires of the system designer that a circuit package be as small as possible, with as few connections as possible, the use of a dedicated pin for self-test mode entry is undesirable. Furthermore, if a dedicated terminal for entering the test mode is provided in packaged form, the user of the memory must take care to ensure that the proper voltage is presented to this dedicated terminal so that the test mode is not unintentionally entered during normal system usage. Accordingly, providing an additional terminal for a chip enable function only during special test modes is not considered desirable. Such a terminal is especially undesirable considering that an additional signal or bias line must be provided to the terminal when the device is installed in a memory system.
Another technique for enabling a special test mode is the application of an illegal condition such as an overvoltage signal at one or more terminals which have other functions during normal operation, such overvoltage indicating that a test mode is to be enabled. This concept is described in U.S. Pat. No. 4,654,849, and in U.S. Pat. No. 4,860,259 (using an overvoltage on an address terminal). Said U.S. Pat. No. 4,860,259 also describes a method which enables a special test mode in a dynamic RAM responsive to an overvoltage condition at the column address strobe terminal followed by the voltage on this terminal falling to a low logic level. The McAdams et al. article, cited hereinabove, describes a method of entering test mode which includes the multiplexing of a test number onto address inputs while an overvoltage condition exists on a clock pin, where the number at the address inputs selects one of several special test modes. Due to its additional complexity, overvoltage enabling of special test modes does add additional security that special test modes will not be entered inadvertently, i.e., relative to the use of a dedicated control terminal for enabling the test modes. However, the approach disadvantageously requires added circuit complexity and costs, while still not guaranteeing against inadvertent activation of a test mode, e.g., resulting from a signal spike.
Thus, a genuine need exists in the art for a novel approach to initiating a special non-functional mode which requires no predefined "illegal condition" to enter or dedicated test pin, and is totally transparent to an end user, as well as employing a disable scheme for the special non-functional mode which guarantees no interference with an end user's functional mode.